Many types of semiconductor devices are fabricated on epitaxial wafers (also known in the industry as “epi” wafers) that contain materially complex, multiple epitaxial layers deposited across a wafer of a desired substrate material. The process of depositing these epitaxial layers, as well as the microstructure of the layers themselves, unavoidably contributes large intrinsic tensile or compressive stresses that produce large physical distortions to the wafer flatness. These distortions are generally known as bow and warp. By their specific American Society for Testing and Materials (ASTM) definitions, “bow” is quantified as the “deviation of the center point of the median surface of a free-unclamped wafer from the median surface reference plane established by three points equally spaced on a circle with a diameter a specified amount less than the nominal diameter of the wafer”, “warp” is quantified as the “difference between the maximum and minimum distances of the median surface of a free, unclamped wafer from a reference plane.” For the sake of convenience, the following discussion refers to a distortion to wafer flatness in the most general sense as “bow.”
Wafer bow often involves more than one of the following root causes: crystallographic lattice mismatch strain between adjacent epitaxial layers; epitaxial microstructure; thermal stress (coefficient of thermal expansion (CTE) mismatch) from the growth processes or high-temperature processing of the epitaxial wafer (e.g., thermal anneal); and additive or subtractive processing of the epitaxial layers during the manufacturing process.
Wafer bow in excess of tens of microns (μm) can negatively impact wafer processing in terms of breakage of wafers. Wafer breakage in semiconductor manufacturing is expensive, as individual wafers contain thousands, or tens of thousands, of product die. The loss of wafers in the manufacturing process due to excessive wafer bow can shut down tools, contaminate equipment, delay shipment schedules, and cost the manufacturer thousands of dollars per wafer.
The presence of bow in “as-purchased” epitaxial wafers prior to beginning any device fabrication can affect the performance of various wafer fabrication tools, such as those used for photolithography, resulting in improper device with critical dimensions that do not meet specifications. Wafer bow values of hundreds of microns or even millimeters make processing very difficult, if not impossible.
The problem of wafer bow becomes greater as the size of the epitaxial wafer increases. Modern gallium arsenide (GaAs) wafer fabrication factories process 6-inch (150 mm) diameter epitaxial wafers, as compared to older, prior art 3-inch (75 mm) and 4-inch (100 mm) wafer sizes.
At the start of wafer processing, wafer bow can be reduced by adding a thick layer of silicon nitride or silicon dioxide to the backside of the epitaxial wafer. However, the formation of this type of dielectric layer requires a relatively high process temperature (e.g., 400° C.), which may result in undesirable modifications of the surface (or sub-surface) epitaxial layers in a pre-processed epitaxial wafer. For example, the stoichiometry of the GaAs may be altered as some of the arsenic (As) present at the surface starts to evaporate when subjected to elevated temperatures for extended periods of time. Additionally, the frontside of the wafer may be contaminated as it comes into direct physical contact with the platen fixtures inside the dielectric deposition tools. As a result, further processing of the surface may be required (e.g., wet cleaning, wet etching, or the like) to ensure that a pristine surface free of damage, impurities, and particles is presented for subsequent device fabrication steps.
Use of stress-controlling dielectrics with post-process, thinned wafers is also of limited value, since the backside of an epitaxial wafer is typically metalized to form an electrical contact to the devices formed on the frontside of the wafer. Adding an insulating layer such as silicon nitride or silicon oxide will therefore interfere with the metal contact layer, making such an approach to wafer bow reduction impractical. Further, the insulator layers are brittle and tend to be relatively thick (up to microns in thickness) and are known to flake and peel off of the backside of the wafer, especially at the wafer edge, resulting in particles that may contaminate wafer frontside processing and interfere with the formation of defect-free devices.